The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7405636 B1

PDF
Full Text
Expired
Date of Patent:
Jul. 29, 2008

Filed:

Apr. 24, 2006
Applicants:

Masayuki Ozasa, Kyoto, JP;

Akio Yokoyama, Osaka, JP;

Manabu Ookubo, Shiga, JP;

Takao Soramoto, Kyoto, JP;

Inventors:

Masayuki Ozasa, Kyoto, JP;

Akio Yokoyama, Osaka, JP;

Manabu Ookubo, Shiga, JP;

Takao Soramoto, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/06 (2006.01); H01L 21/822 (2006.01);
U.S. Cl.
CPC ...
Abstract

Four input nodes I-Ifor inputting 4-phase signals, four resistors R-R, four capacitors C-C, and four output nodes O-Ofor outputting 4-phase signals are provided. The resistors and the capacitors are connected alternately in a loop, and the input nodes and output nodes are connected alternately to the respective nodes between the resistors and the capacitors sequentially. Each of the four resistors is composed of a group of three or more partial resistors, and three groups of the partial resistors R-R, R-Rand R-Rare collected respectively and arranged in the same attitude, while the partial resistors R-Rof the remaining group are distributed into the other groups and arranged in the same line the same attitude as the partial resistors of each of the other groups. The regions of the thus collected groups are arranged in one direction. By simplifying the layout of the components and the shape of the wirings, influences on the characteristics by the parasitic elements are reduced, and complication in the layout and wirings can be suppressed even when using plural stages.


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