Reset control circuit and reset control method

Abstract

To present a reset control circuit and a reset control method used in a system including clock synchronous circuit, capable of resetting appropriately, especially in case of abnormality, when the clock signal is stopped or its period is longer as compared with the reset response required for detection of abnormal state. A reset control circuitfor output control of reset signal RS depending on reset request signal RR comprises a clock transforming unitfor transforming and issuing a clock signal CK, while generating a clock output signal RC at delay of clock output waiting period DC depending on the reset request signal RR, and a reset signal generatorfor generating a reset signal RS at delay of reset output waiting period D depending on the clock output signal RC.