The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2008
Filed:
Aug. 21, 2006
John Banning, Sunnyvale, CA (US);
H. Peter Anvin, San Jose, CA (US);
Robert Bedichek, Palo Alto, CA (US);
Guillermo J. Rozas, Los Gatos, CA (US);
Andrew Shaw, Sunnyvale, CA (US);
Linus Torvalds, Santa Clara, CA (US);
Jason Wilson, San Francisco, CA (US);
John Banning, Sunnyvale, CA (US);
H. Peter Anvin, San Jose, CA (US);
Robert Bedichek, Palo Alto, CA (US);
Guillermo J. Rozas, Los Gatos, CA (US);
Andrew Shaw, Sunnyvale, CA (US);
Linus Torvalds, Santa Clara, CA (US);
Jason Wilson, San Francisco, CA (US);
Transmeta Corporation, Santa Clara, CA (US);
Abstract
A method of translating instructions from a target instruction set to a host instruction set. In one embodiment, a plurality of first target instructions is translated into a plurality of first host instructions. After the translation, it is determined whether the plurality of first target instructions has changed. A copy of a second plurality of target instructions is stored and compared with the plurality of first target instructions if the determining slows the operation of the computer system. After comparing, the plurality of first host instructions is invalidated if there is a mismatch. According to one embodiment, the storing, the comparing and the invaliding is initiated when the determining indicates that a page contains at least one change to the plurality of first target instructions. In one embodiment, the determining is by examining a bit indicator associated with a memory location of the plurality of first target instructions.