The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2008
Filed:
May. 31, 2005
Chooi Pei Lim, Penang, MY;
Joo Ming Too, Kedah, MY;
Yew Fatt (Edwin) Kok, Penang, MY;
Kar Keng Chua, Penang, MY;
Chooi Pei Lim, Penang, MY;
Joo Ming Too, Kedah, MY;
Yew Fatt (Edwin) Kok, Penang, MY;
Kar Keng Chua, Penang, MY;
Altera Corporation, San Jose, CA (US);
Abstract
Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.