The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 22, 2008

Filed:

Mar. 31, 2005
Applicants:

Clement R. Yonker, Kennewick, WA (US);

Dean W. Matson, Kennewick, WA (US);

Daniel J. Gaspar, Richland, WA (US);

George S. Deverman, Richland, WA (US);

Inventors:

Clement R. Yonker, Kennewick, WA (US);

Dean W. Matson, Kennewick, WA (US);

Daniel J. Gaspar, Richland, WA (US);

George S. Deverman, Richland, WA (US);

Assignee:

Battelle Memorial Institute, Richland, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/445 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods are disclosed for depositing materials selectively and controllably from liquid, near-critical, and/or supercritical fluids to a substrate or surface controlling the location and/or thickness of material(s) deposited to the surface or substrate. In one exemplary process, metals are deposited selectively filling feature patterns (e.g., vias) of substrates. The process can be further used to control deposition of materials on sub-surfaces of composite or structured silicon wafers, e.g., for the deposition of barrier films on silicon wafer surfaces. Materials include, but are not limited to, overburden materials, metals, non-metals, layered materials, organics, polymers, and semiconductor materials. The instant invention finds application in such commercial processes as semiconductor chip manufacturing. In particular, selective deposition is envisioned to provide alternatives to, or decrease need for, such processes as Chemical Mechanical Planarization of silicon surfaces in semiconductor chip manufacturing due to selective filling and/or coating of pattern features with metals deposited from liquid, near-critical, or supercritical fluids.


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