The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 22, 2008
Filed:
Jan. 17, 2006
Raymond C. Pang, San Jose, CA (US);
Trevor J. Bauer, Boulder, CO (US);
F. Erich Goetting, Cupertino, CA (US);
Bruce E. Talley, Louisville, CO (US);
Steven P. Young, Boulder, CO (US);
Raymond C. Pang, San Jose, CA (US);
Trevor J. Bauer, Boulder, CO (US);
F. Erich Goetting, Cupertino, CA (US);
Bruce E. Talley, Louisville, CO (US);
Steven P. Young, Boulder, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method of providing a family of integrated circuits (ICs) includes applying a first product selection code (PSC) to a first IC die, applying a second PSC to a second IC die, and providing a third packaged IC die. The first IC die includes first and second portions, both of which are operational based on the first PSC. The second IC die is a duplicate of the first die, but the second portion is rendered non-operational by the second PSC. The third IC die is substantially similar to the first portion of the first die. The second and third packages can be the same and the packaged dies can be interchangeable in a system. When the dies are programmable logic device (PLD) dies, the second and third dies use the same configuration bit stream, which may be smaller than the configuration bit stream for the first IC die.