The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2008
Filed:
Apr. 04, 2006
Robert C. Thaden, Austin, TX (US);
Steven C. Hesley, Austin, TX (US);
Christopher B. Ang, Austin, TX (US);
Jeffery E. Short, Austin, TX (US);
Eric W. Mahurin, Austin, TX (US);
Robert C. Thaden, Austin, TX (US);
Steven C. Hesley, Austin, TX (US);
Christopher B. Ang, Austin, TX (US);
Jeffery E. Short, Austin, TX (US);
Eric W. Mahurin, Austin, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A method for designing integrated circuits may include custom designing, at the transistor level, individual cells to be incorporated into cell-based macros. A macro-level function of an integrated circuit's design specification requiring custom, transistor-level design may be identified and custom cells may be designed at the transistor-level to meet the design specification. Custom designed cells may be included in cell-based macros, thus allowing cell-based simulation and verification methodologies and tools to be used on the integrated circuit design. Static timing analysis, circuit extraction and other characteristics may be defined for each custom cell and the timing analysis and circuit extraction for cell-based macros may be defined based on the timing and extraction information for the custom cells included in the macro.