The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2008
Filed:
Jan. 26, 2004
Takamitsu Yamada, Kanagawa-Ken, JP;
Yasutaka Tsukamoto, Kanagawa-Ken, JP;
Hidetaka Minami, Kanagawa-Ken, JP;
Takamitsu Yamada, Kanagawa-Ken, JP;
Yasutaka Tsukamoto, Kanagawa-Ken, JP;
Hidetaka Minami, Kanagawa-Ken, JP;
Ricoh Company, Ltd., Tokyo, JP;
Abstract
A method for performing scan test on a semiconductor integrated circuit including at least two blocks to be tested. The method includes isolating each of the at least two blocks to be tested exclusively from further blocks; and supplying a plurality of scan clocks having different phases each to each of the at least two blocks. In addition, a semiconductor integrated circuit includes at least two blocks to be tested, an Core Wrapper Architecture isolation unit for isolating each of the at least two blocks to be tested exclusively from further blocks, and an input terminal for inputting a plurality of scan clocks each to each of the at least two blocks, in which a Wrapper register included in the Core Wrapper Architecture is configured to be supplied selectively with one of a scan clock and a system clock for the blocks.