The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2008

Filed:

Aug. 11, 2000
Applicants:

William J. Dally, Stanford, CA (US);

W. Patrick Hays, Cambridge, MA (US);

Robert Gelinas, Needham, MA (US);

Sol Katzman, Waltham, MA (US);

Sam Rosen, Los Angeles, CA (US);

Staffan Ericsson, Brookline, MA (US);

Inventors:

William J. Dally, Stanford, CA (US);

W. Patrick Hays, Cambridge, MA (US);

Robert Gelinas, Needham, MA (US);

Sol Katzman, Waltham, MA (US);

Sam Rosen, Los Angeles, CA (US);

Staffan Ericsson, Brookline, MA (US);

Assignee:

MIPS Technologies, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 15/80 (2006.01); G06F 15/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seem less transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions of RISC instruction sets. The DSP superscalar architecture also provides memory pointers with hardware circular buffer support, an interruptible and nested zero-overhead loop counter, and prioritized low-overhead interrupts.


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