The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 15, 2008

Filed:

Jun. 26, 2003
Applicants:

Benjamin Thomas Percer, Roseville, CA (US);

Naysen Jesse Robertson, Orangeville, CA (US);

Akbar Monfared, Placerville, CA (US);

Inventors:

Benjamin Thomas Percer, Roseville, CA (US);

Naysen Jesse Robertson, Orangeville, CA (US);

Akbar Monfared, Placerville, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 27/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a voltage margin testing system incorporated in an electronic system, such as, a computer system (e.g., a server), having a plurality of components for at least some of which voltage margin testing is required. A voltage margin testing of the invention can include a controller, such as a Baseboard Management Controller (BMC), internal to the computer system and a digital voltage adjuster, e.g., a digital potentiometer, that is in communication with the controller. The voltage adjuster can effect generation of one or more test voltages, for example, by varying resistance in a feedback circuitry of a regulator whose output voltage is applied to system components, for application to the components in response to commands from the controller.


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