The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2008
Filed:
Oct. 05, 2006
Evgeny Pikhay, Migdal Haemek, IL;
Yakov Roizin, Migdal Haemek, IL;
Alexey Heiman, Migdal Haemek, IL;
Amos Fenigstein, Migdal Haemek, IL;
Evgeny Pikhay, Migdal Haemek, IL;
Yakov Roizin, Migdal Haemek, IL;
Alexey Heiman, Migdal Haemek, IL;
Amos Fenigstein, Migdal Haemek, IL;
Tower Semiconductor Ltd., Migdal Haemek, IL;
Abstract
The efficient removal of parasitic electron charges from the ONO structure of an NROM cell by periodically applying a negative gate refresh voltage in a way that injects holes from the substrate into the ONO structure. Initially, after each erase pulse is generated and an unacceptable erase state is detected, the erase pulse magnitude is incrementally increased to compensate for the increasing parasitic electrons. When a predetermined maximum drain voltage is reached, the negative gate refresh voltage is applied to refresh the ONO structure, and the drain voltage is reset to an initial state. A novel NROM cell uses a P+ doped polysilicon gate or Top Oxide produced with a high-k dielectric (Alumina) to facilitate blocking the injection of gate electrons, and the Bottom Oxide thickness is selectively thinned to increase hole injection.