The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2008
Filed:
Aug. 07, 2007
Cheng-hsiung Huang, Cupertino, CA (US);
Guu Lin, San Jose, CA (US);
Shih-lin S. Lee, San Jose, CA (US);
Chih-ching Shih, Pleasanton, CA (US);
Irfan Rahim, San Jose, CA (US);
Stephanie T. Tran, San Jose, CA (US);
Cheng-Hsiung Huang, Cupertino, CA (US);
Guu Lin, San Jose, CA (US);
Shih-Lin S. Lee, San Jose, CA (US);
Chih-Ching Shih, Pleasanton, CA (US);
Irfan Rahim, San Jose, CA (US);
Stephanie T. Tran, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Integrated circuits are provided that have sensitive circuitry such as programmable polysilicon fuses. Electrostatic discharge (ESD) protection circuitry is provided that prevents damage or undesired programming of the sensitive circuitry in the presence of an electrostatic discharge event. The electrostatic discharge protection circuitry may have a power ESD device that limits the voltage level across the sensitive circuitry to a maximum voltage and that draws current away from the sensitive circuitry when exposed to ESD signals. The electrostatic discharge protection circuitry may also have an ESD margin circuit that helps to prevent current flow through the sensitive circuitry when the maximum voltage is applied across the sensitive circuitry.