The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2008
Filed:
Aug. 29, 2005
Joseph Storniolo, Aliso Viejo, CA (US);
Jeremy Monroe, Aliso Viejo, CA (US);
Melanie Daniels, Folsom, CA (US);
William Veitschegger, Folsom, CA (US);
Michael Hrybenko, Syosset, NY (US);
Frank Kimmey, Sacramento, CA (US);
Joseph Storniolo, Aliso Viejo, CA (US);
Jeremy Monroe, Aliso Viejo, CA (US);
Melanie Daniels, Folsom, CA (US);
William Veitschegger, Folsom, CA (US);
Michael Hrybenko, Syosset, NY (US);
Frank Kimmey, Sacramento, CA (US);
Powerwave Technologies, Inc., Santa Ana, CA (US);
Abstract
A high power, low loss RF strip transmission line coupling structure is provided. It includes a multi-layer printed circuit board (PCB), a top cover and a bottom cover. The top and bottom covers provide the ground reference for the strip transmission line coupling structure. The PCB is fastened to the top and bottom covers and is used for: creating the center conductor of an air dielectric strip transmission line and edge coupler; providing a means to transition from microstrip to air dielectric strip transmission line; supporting the air dielectric strip transmission line; routing of other signals; and passing ground to the top and bottom covers. To create an air dielectric strip transmission line, the PCB material is adequately removed to effectively form a rectangular bar of dielectric and metal layers. This rectangular bar is plated along the edges where the PCB material was removed to ensure that the top and bottom PCB metal layers are at the same potential.