The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2008

Filed:

Jul. 13, 2005
Applicants:

Hoai V. Tran, Gilroy, CA (US);

Kevin Jerome Rowett, Cupertino, CA (US);

Somsubhra Sikdar, San Jose, CA (US);

Jonathan Sweedler, Los Gatos, CA (US);

Caveh Jalali, Redwood City, CA (US);

Inventors:

Hoai V. Tran, Gilroy, CA (US);

Kevin Jerome Rowett, Cupertino, CA (US);

Somsubhra Sikdar, San Jose, CA (US);

Jonathan Sweedler, Los Gatos, CA (US);

Caveh Jalali, Redwood City, CA (US);

Assignee:

Mistletoe Technologies, Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory subsystem includes multiple different caches configured for different types of data transfer operations between one or more processing units and a main memory. The different caches can include a first general cache configured for general random memory accesses, a software controlled cache used for controlling cache operations for different processing devices accessing the same data, and a streaming cache configured for large packet data memory accesses. An arbiter may be used for arbitrating requests by the multiple different caches for accessing the main memory.


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