The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2008

Filed:

Apr. 30, 2003
Applicants:

Babu Kalampukattussery Cherian, Bangalore, IN;

William R. Krieg, Cary, NC (US);

Shreedhara Maduvinakodi Ramegowda, Bangalore, IN;

Hemant Kumar Kashinathrao Revankar, Bangalore, IN;

Andrew T. Schnable, Cary, NC (US);

Shiva Kumar Yenigalla, Bangalore, IN;

Inventors:

Babu Kalampukattussery Cherian, Bangalore, IN;

William R. Krieg, Cary, NC (US);

Shreedhara Maduvinakodi Ramegowda, Bangalore, IN;

Hemant Kumar KashinathRao Revankar, Bangalore, IN;

Andrew T. Schnable, Cary, NC (US);

Shiva Kumar Yenigalla, Bangalore, IN;

Assignee:

Lucent Technologies Inc., Murray Hill, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

Multiple fiber channel (FC) storage area networks (SANs) are interconnected over wide-area networks (WANs) to form a long-distance (e.g., greater than about 10 km) distributed storage area network (DSAN) that includes FC to Internet Protocol (IP) over WAN (e.g., SONET or gigabit Ethernet (GE)) gateways that interwork the FC buffer-to-buffer and IP/WAN flow-control mechanisms appropriate to either the SONET or GE link layers using an additive increase, multiplicative decrease (AIMD) congestion avoidance algorithm. The gateways effectively spoof the FC buffer-to-buffer credit mechanism on the FC-interface side of the gateway, while using an IP Internet control message protocol (ICMP) quench mechanism on all WAN links and additionally the IEEE 802.3 pause packet flow control mechanism on gigabit Ethernet (GE) WAN links in combination, in both cases, with a rate-throttling mechanism at the FC<->IP converter.


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