The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2008

Filed:

Feb. 02, 2007
Applicant:

Glenn E. Starnes, Austin, TX (US);

Inventor:

Glenn E. Starnes, Austin, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory has a first memory block, a second memory block, a data bus, a first sense amplifier, a second sense amplifier, a first circuit, and a second circuit. The first sense amplifier is coupled to the first memory block. The second sense amplifier is coupled to the second memory block. The first circuit is coupled to the data bus and the first sense amplifier. The first circuit switches from precharging the data bus to providing data when the first memory block is selected and is decoupled from the data bus in response to the first memory block being deselected. The second circuit is coupled to the data bus and the second sense amplifier. The second circuit switches from precharging the data bus to providing data when the second memory block is selected and is decoupled from the data bus in response to the second memory block being deselected.


Find Patent Forward Citations

Starnes, Glenn. (2008). Multiple block memory with complementary data path (U.S. Patent No. 7397722). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7397722

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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