Internal voltage level control circuit and semiconductor memory device as well as method of controlling the same

Abstract

There are provided a voltage level control circuit with a reduced power consumption and a method of controlling the same. When a signal 'A' is in a 'L' level and a signal PL entered from the outside of the voltage level control circuit becomes “H” level, a latch signal La outputted from a latch () becomes “H” level, whereby NFETs () turn ON. A voltage dividing circuit comprising resistances () and current mirror differential amplifiers () are placed in active states to output “H” as a signal A which controls a boost voltage Vbt (word line driving voltage. As the boost voltage Vbt is increased and reaches to a reference voltage Vref, a voltage Vbecomes “H”, whereby the signal A becomes “L”. After the signal A become “L”, the latch () is made through. At this time, the signal PL is “L”, the latch signal La outputted from the latch () becomes “L”, whereby the NFETs () turn OFF. As described here, the NFETs () is kept OFF in the other time period than when needed, in order to reduce the power consumption.