The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2008

Filed:

Oct. 12, 2005
Applicants:

Sean Christopher Erickson, Fort Collins, CO (US);

Jason Dee Hudson, Eaton, CO (US);

Inventors:

Sean Christopher Erickson, Fort Collins, CO (US);

Jason Dee Hudson, Eaton, CO (US);

Assignee:

LSI Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/425 (2006.01);
U.S. Cl.
CPC ...
Abstract

A deep n-well is formed beneath the area of a capacitor structure. The use of a deep n-well lessens the parasitic capacitance by placing a diode in series with the interlayer dielectric cap. The deep n-well also reduces substrate noise. Once the n-well is implanted and annealed, a cross hatch of shallow trench isolation is patterned over the n-well. The shallow trench isolation reduces and confines the inductively and/or capacitively coupled surface currents to small areas that are then isolated from the rest of the chip.


Find Patent Forward Citations

Erickson, Sean. (2008). Apparatus to passivate inductively or capacitively coupled surface currents under capacitor structures (U.S. Patent No. 7397105). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7397105

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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