The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2008

Filed:

Dec. 13, 2006
Applicant:

Jae Jung Lee, Seoul, KR;

Inventor:

Jae Jung Lee, Seoul, KR;

Assignee:

Hynix Semiconductor Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of forming a semiconductor memory device includes providing a semiconductor substrate having a cell region and a peripheral region. A gate dielectric layer is formed over the semiconductor substrate in the peripheral region. An insulating layer is formed over the gate dielectric layer. An isolation trench is formed in the peripheral region, the isolation trench defining first and second trenches having different opening widths. A first gap-fill layer is provided over the isolation trench and on the step. The first gap-fill layer has a first portion on a sidewall of the insulating layer, a second portion on a sidewall of the gate dielectric layer, and a third portion at least partly filling the second trench of the isolation trench, the second portion being thicker than the first portion. A wet etch is performed to remove at least part of the first gap-fill layer. A second gap-fill layer is provided over the first gap-fill layer in the isolation trench to form an isolation structure. The second portion of the first gap-fill layer is configured to protect the gate dielectric layer during the wet etch step.


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