The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 01, 2008

Filed:

Aug. 03, 2004
Applicants:

Hiroaki Mochizuki, Chino, JP;

Masahide Uchida, Suwa, JP;

Yasuji Yamasaki, Chino, JP;

Inventors:

Hiroaki Mochizuki, Chino, JP;

Masahide Uchida, Suwa, JP;

Yasuji Yamasaki, Chino, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

Aspects of the invention can provide an electro-optical device having n image signal lines to which n serial to parallel converted image signals are supplied. A driving circuit has a sampling circuit that can include a plurality of thin film transistors. Each of the thin film transistors can have (i) a drain connected to a drain wiring line arranged from a data line in a direction in which the data line extends, (ii) a source connected to a source wiring line arranged from the image signal line in a direction in which the data line extends, and (iii) a gate arranged to be sandwiched between the drain wiring line and the source wiring line in a direction in which the data line extends, and the plurality of thin film transistors can be arranged to correspond to the plurality of data lines. Two adjacent thin film transistors with the boundary between thin film transistor groups interposed therebetween among the plurality of thin film transistors can be arranged such that the arrangements of the source and drain wiring lines with a gate interposed therebetween are opposite to each other. By doing so, it is possible to reduce image faults caused by parasitic capacitance located between the thin film transistors in the sampling circuit.


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