The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2008
Filed:
Apr. 14, 2005
Takayoshi Shimazawa, Kawasaki, JP;
Takayoshi Shimazawa, Kawasaki, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A semiconductor circuit allows a timing adjustment after detailed routing without rearrangement and rerouting, an adjustment of delay variance due to process variation, and a delay adjustment even after chip formation using a primitive cell with a built-in means for adjusting delay time. The circuit connected between an input pad and an output pad, an operating method for the same, and a delay time control system circuit, which externally adjusts delay time of a plurality of control terminal-equipped/variable capacitance embedded buffers configures a semiconductor circuit. The structure includes: a first buffer connected between the input pad and the output pad; and a plurality of capacitances connectable in parallel between a fixed potential and a current flowing path, which is positioned between the first buffer and the output pad, and that controls connection between each of the plurality of capacitances and the output pad.