The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 24, 2008

Filed:

Jun. 30, 2005
Applicants:

Uwe Fassnacht, Sunnyvale, CA (US);

Juergen Koehl, Weil im Schoenbuch, DE;

Inventors:

Uwe Fassnacht, Sunnyvale, CA (US);

Juergen Koehl, Weil im Schoenbuch, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of routing an interconnect metal layer of an integrated circuit, wherein single-width nets are replicated and routed in parallel to reduce the total resistance on the net; wide wires are decomposed into a several single-width wires routed in parallel to improve uniformity of metal interconnect routing and therefore manufacturability of metal interconnect layers. The decomposition step is performed during a preliminary wire route after initial physical placement. Access to pin shapes is ensured through a branching and a recombination of the parallel single-width wires. Separate wire segments are rejoined at the source and sink of the net. The parallel wire segments do not change the logic behavior of the circuit.


Find Patent Forward Citations

Quick Actions:

Fassnacht, Uwe. (2008). Regular routing for deep sub-micron chip design (U.S. Patent No. 7392497). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7392497

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…