Testing ram address decoder for resistive open defects

Abstract

Hard-open defects between logic gates of, for example, an address decoder and the voltage supply which result in logical and sequential delay behavior render a memory conditionally inoperative. A method and apparatus for testing integrated circuits for these types of faults is proposed, in which two cells of two logically adjacent rows or columns are written with complementary logic data. If a read operation reveals the data in the two cells to be identical, the presence and location of a hard-open defect is demonstrated. The read and write operations each occur as a result of a clock pulse, and the method includes the steps of setting a clock cycle such that, in the event that said first cell is demonstrating slow-to-fall behavior, the reading cycle will be caused to be performed before the logic state of said first cell has fallen to its minimum level, and/or of setting the width of said clock pulses such that, in the event that the first cell is demonstrating slow-to-rise behavior, the reading cycle will be caused to be performed before the logic state of said first cell has risen to its maximum level.