The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2008
Filed:
Jun. 17, 2005
Tuyet Ngoc Simmons, Los Gatos, CA (US);
Brian Sadler, San Jose, CA (US);
Tuyet Ngoc Simmons, Los Gatos, CA (US);
Brian Sadler, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Testing an integrated circuit having programmable logic is described. Programmable logic is configured as a daisy-chain of registers (-through-(N+1)) in a closed input/output loop to register a logic 1 and logic 0s. The logic states are circulated around the closed input/output loop. Operation of output blocks (-through-N) is controlled responsive to a series of outputs (-through-N) provided from a portion of the daisy-chain of registers (-through-N) to selectively place an output block of output blocks (-through-N) in an output mode responsive to the logic 1 output in the series of outputs while leaving the output blocks remaining in a non-output mode responsive to the logic 0s in the series of outputs. The output blocks (-through-N) are commonly coupled at an output node () for coupling to a single test channel, as only one output block is in the output mode at a time.