The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 24, 2008
Filed:
Dec. 27, 2005
David Lewis, Toronto, CA;
Paul Leventis, Toronto, CA;
Vaughn Betz, Toronto, CA;
Thomas Yau-tsun Wong, Markham, CA;
Andy Lee, San Jose, CA (US);
Philip Pan, Fremont, CA (US);
David Lewis, Toronto, CA;
Paul Leventis, Toronto, CA;
Vaughn Betz, Toronto, CA;
Thomas Yau-Tsun Wong, Markham, CA;
Andy Lee, San Jose, CA (US);
Philip Pan, Fremont, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Circuitry for facilitating the use of the memory elements in the look-up tables ('LUTs') of a field programmable gate array ('FPGA') as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.