Self-aligning patterning method

Abstract

The present invention relates to a self-aligning patterning method which can be used to manufacture a plurality of multi-layer thin film transistors on a substrate. The method comprises firstly forming a patterned maskon the surface of a sacrificial layerwhich is part of a multi-layer structurewhich comprises the substrate, a conductive layer, an insulating layerand the sacrificial layer. Unpatterned areas are then etched to remove the corresponding areas of the sacrificial layer, the insulating layerand the conductive layerthereby leaving voids. A layer of dielectricis then deposited over the etched multi-layer structure to at least substantially fill the voids. The deposited dielectric is then etched in order to at least partially expose the sides of the remaining areasof the sacrificial layer. Conductive materialis then deposited on the surface of the etched dielectric. Finally, the remaining areasof the sacrificial layer are removed together with any overlying material. The resulting plurality of multi-layer thin film transistors is preferably in the form of an array which may in turn be formed into a display device by coupling each transistor in the array to a light-emitting cell.