Method of patterning elements within a semiconductor topography

Abstract

A method is provided which includes forming a hardmask feature adjacent to a patterned sacrificial structure of a semiconductor topography, selectively removing the patterned sacrificial structure to expose a lower layer and etching exposed portions of the lower layer in alignment with the hardmask feature. In some embodiments, forming the hardmask feature may include conformably depositing a hardmask material above the patterned sacrificial structure and lower layer as well as blanket etching the hardmask material such that upper surfaces of the patterned sacrificial structure and portions of the lower layer are exposed and portions of the hardmask material remain along sidewalls of the patterned sacrificial structure. The method may be applied to produce an exemplary semiconductor topography including a plurality of gate structures each having a width less than approximately 70 nm, wherein a variation of the widths among the plurality of gate structures is less than approximately 10%.