The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2008

Filed:

Oct. 20, 2005
Applicant:

Jon Udell, West Linn, OR (US);

Inventor:

Jon Udell, West Linn, OR (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract

Circuit test algorithms, or portions thereof, can be executed in a non-sequential manner over a network comprising a plurality of processors. Such distributed processing can improve the speed with which results are obtained and processed. Circuit testing algorithms can include, but are not limited to, test pattern generation algorithms and fault simulation algorithms. Those algorithms that are independent from each other can be executed non-sequentially (e.g., in parallel). Allocation of the various algorithm portions for execution among various processors can be based in part on a queue length associated with the processor. The queue length is adjustable based on many factors including data indicating the status of an execution maintained by the controlled processors. The faster processors can have their queue lengths increased. Multiple queue lengths can be maintained to allow for changes in allocation based on the granularity of tasks being performed by the controlling processor.


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