The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2008

Filed:

Dec. 15, 2005
Applicants:

Michael J. Corrigan, Rochester, MN (US);

Paul Luverne Godtland, Rochester, MN (US);

Joaquin Hinojosa, Round Rock, TX (US);

Cathy May, Millwood, NY (US);

Naresh Nayar, Rochester, MN (US);

Edward John Silha, Austin, TX (US);

Inventors:

Michael J. Corrigan, Rochester, MN (US);

Paul LuVerne Godtland, Rochester, MN (US);

Joaquin Hinojosa, Round Rock, TX (US);

Cathy May, Millwood, NY (US);

Naresh Nayar, Rochester, MN (US);

Edward John Silha, Austin, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more 'hint bits' are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.


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