The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 17, 2008
Filed:
Oct. 31, 2005
Keith Grimes, Colorado Springs, CO (US);
Todd Jeffrey Egbert, Colorado Springs, CO (US);
Edmund Paul Fehrman, Monument, CO (US);
Keith Grimes, Colorado Springs, CO (US);
Todd Jeffrey Egbert, Colorado Springs, CO (US);
Edmund Paul Fehrman, Monument, CO (US);
LSI Corporation, Milpitas, CA (US);
Abstract
An automated system for validating Peripheral Component Interconnect (PCI) bus adapters or PCI-X bus adapters has a computer, motherboard, a PCI-X bus and isolated test slot for operatively coupling a PCI/PCI adapter under test through the PCI-X bus to the motherboard. The isolated test slot is adapted and arranged to minimize degradation of data flow on the PCI-X bus such that a PCI-X adapter, mounted in the isolated test slot, can negotiate a required operating rate greater than PCI operating rates. It can be configured as a low profile slot in a low profile computer system, such as a 2U low profile system. A method for validating the PCI/PCI-X bus adapters comprises operatively coupling the bus adapter under test to the motherboard, negotiating to the required operating rate and testing the functionality of the adapter. The operating rate of the bus adapter can be verified to ensure the PCI/PCI-X bus adapters are tested at required PCI/PC-X rates.