High-speed adaptive interconnect architecture with nonlinear error functions

Abstract

A low cost and high speed equalizing receiver structure is provided for improved inter-chip and inter-module communications. The receiver is able to recover data from a corrupted waveform from a signal wire such as one found on data, address or control wires in a microsystem architecture. The receiver can be used with binary as well as m-ary pulse amplitude modulation schemes. The receiver can be used to increase the sustainable data rate between chips or can be used to sustain a given data rate over a poorer quality channel as compared to prior art interconnect technologies. Methods for training and operating the receiver structure are provided. A novel structure called the decision feedback equalizer and cross talk canceller (DFE-CTC) is introduced and methods to compute the coefficients to minimize error in terms of the lnorm, the lnorm, and statistical probability of error functions are also disclosed.