The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7388416 B1

PDF
Full Text
Expired
Date of Patent:
Jun. 17, 2008

Filed:

Jul. 25, 2005
Applicant:

Masazumi Marutani, Kawasaki, JP;

Inventor:

Masazumi Marutani, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 3/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A latch circuit includes a voltage driven type data reading unit and a voltage driven type data holding unit, and operates based on a clock signal that is supplied from an outside source. The data reading unit reads both a first input data and a second input data, and outputs both a first output data and a second output data based on both the first input data and the second input data, while the data holding unit holds both the first output data and the second output data. Both the first input data and the second input data are differential signals, and both the first output data and the second output data are differential signals that have phases that are inverted.


Find Patent Forward Citations

Marutani, Masazumi. (2008). Latch circuit, 4-phase clock generator, and receiving circuit (U.S. Patent No. 7388416). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7388416

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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