The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2008

Filed:

Nov. 13, 2006
Applicants:

Shih-chang Chang, Hsinchu, TW;

De-hua Deng, Ba-De, TW;

Chun-hsiang Fang, Yilan Hsien, TW;

Yaw-ming Tsai, Taichung Hsien, TW;

Inventors:

Shih-Chang Chang, Hsinchu, TW;

De-Hua Deng, Ba-De, TW;

Chun-Hsiang Fang, Yilan Hsien, TW;

Yaw-Ming Tsai, Taichung Hsien, TW;

Assignee:

TFO Displays Corp., Chu-Nan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A thin film transistor (TFT) with a self-aligned lightly-doped region and a fabrication method thereof. An active layer has a channel region, a first doped region and a second doped region, in which the first doped region is disposed between the channel region and the second doped region. A gate insulating layer formed overlying the active layer has a central region, a shielding region and an extending region. The shielding region is disposed between the central region and the extending region, the central region covers the channel region, the shielding region covers the first doped region, and the extending region covers the second doped region. The shielding region is thicker than the extending region. A gate layer is formed overlying the gate insulating layer, covers the central region and exposes the shielding region and the extending region.


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