The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 17, 2008

Filed:

Sep. 24, 2004
Applicants:

Do-hyung Kim, Seoul, KR;

Jin-ho Kim, Kyunggi-do, KR;

Byung-jun Hwang, Kyunggi-do, KR;

Inventors:

Do-Hyung Kim, Seoul, KR;

Jin-Ho Kim, Kyunggi-do, KR;

Byung-Jun Hwang, Kyunggi-do, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device having LDD-type source/drain regions and a method of fabricating the same are provided. The semiconductor device includes at least a pair of gate patterns disposed on a semiconductor substrate and LDD-type source/drain regions disposed at both sides of the gate patterns. The substrate having the gate patterns and the LDD-type source/drain regions is covered with a conformal etch stop layer. The etch stop layer is covered with an interlayer insulating layer. The LDD-type source/drain region is exposed by a contact hole that penetrates the interlayer insulating layer and the etch stop layer. The method of forming the LDD-type source/drain regions and the etch stop layer includes forming low-concentration source/drain regions at both sides of the gate patterns and forming the conformal etch stop layer on the substrate having the low-concentration source/drain regions. Gate spacers are then formed on the sidewalls of the gate patterns. Using the gate patterns and the gate spacers as implantation masks, impurity ions are implanted into the semiconductor substrate to form high-concentration source/drain regions. The spacers are then selectively removed. An interlayer insulating layer is formed on the substrate where the spacers are removed.


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