The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2008
Filed:
Jun. 08, 2006
Yong Zhu, Albuquerque, NM (US);
Jorge Ernesto Carrillo, San Jose, CA (US);
Yong Zhu, Albuquerque, NM (US);
Jorge Ernesto Carrillo, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method is provided for building a simulation environment. A first functional model is produced that emulates the interaction of a processor with a first interface of a bus for the processor as controlled by a first script. A second functional model is produced that is controllable to emulate multiple interfaces. The second functional model is controlled to emulate a second interface of an input/output peripheral by a second script. A third functional model is produced that emulates a memory subsystem. A simulation environment is automatically generated that simulates the design block for a programmable logic device. The simulation environment couples the bus to the design block and the first and third functional models, couples the second interface to the design block and the second functional model, and couples the first and second functional models via a synchronization bus used for synchronizing between transactions of the first and second scripts.