The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2008
Filed:
May. 14, 2003
Ralf Arnold, Poing, DE;
Matthias Heinitz, Munich, DE;
Siegmar Köppe, Laatzen, DE;
Volker Schöber, Hannover, DE;
Ralf Arnold, Poing, DE;
Matthias Heinitz, Munich, DE;
Siegmar Köppe, Laatzen, DE;
Volker Schöber, Hannover, DE;
Infineon Technologies AG, Munich, DE;
Abstract
In order to test digital modules with functional elements, these are divided into test units () which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of the test unit (), and the test responses resulting from this are evaluated at the outputs of the test unit (). The effect is then encountered that changes at each of the inputs of a test unit () do not all affect a particular output of this test unit (). For every output of the test unit (), it is possible to define a cone () whose apex is formed by the particular output of the test unit () and whose base comprises the inputs of the test unit () where, and only where, changes affect the particular output. According to the invention, the test pattern to be applied to the inputs of the test unit () is constructed of sub-patterns, whose length is in particular ≦ the number of inputs of the test unit () that are contained in the base of a cone (). Owing to their shorter length, all possible combinations can be used for selecting the sub-patterns, so that a comprehensive function test of the test unit () can be carried out rapidly and with little outlay. In a digital module, this test function may in particular be implemented by a self-test unit () which can switch over the rest of the digital module into a test mode, generates the test patterns on the basis of sub-patterns, loads them into a test-pattern output register () for application to a test unit () and can evaluate the test response subsequently found at the outputs of the test unit () by means of an evaluation unit (), or read it in for evaluation.