The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2008
Filed:
Feb. 26, 2004
Mitrajit Chatterjee, San Jose, CA (US);
Ming Tang, Fremont, CA (US);
Peter Z. Onufryk, Flanders, NJ (US);
Steven Chau, Fremont, CA (US);
Mitrajit Chatterjee, San Jose, CA (US);
Ming Tang, Fremont, CA (US);
Peter Z. Onufryk, Flanders, NJ (US);
Steven Chau, Fremont, CA (US);
Integrated Device Technology, Inc., San Jose, CA (US);
Abstract
A memory unit includes a memory organized into protected and non-protected areas. A controller manages access to the memory so that the protected area can be written to through a JTAG or CPU interface. Once written to, the protected area is only accessible to particular logic and cannot be over-written until the entire memory is erased. The controller is configured to allow a BCV to be stored in the memory through either the JTAG or CPU interface. The controller is also configured to allow writing to the protected area and boot configuration vector in memory before CPU boot-up by using a JTAG clock signal provided through an external pin when a system clock signal is not available. A reset circuit generates one or more initialization signals using either the BCV from memory or another BCV provided on external BCV pins, depending upon whether another external BCV pin is asserted.