The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 10, 2008
Filed:
Feb. 26, 2007
Jun Wan, Wilmington, MA (US);
Peter R. Holloway, North Andover, MA (US);
Jun Wan, Wilmington, MA (US);
Peter R. Holloway, North Andover, MA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A buffer circuit () including a first half circuit and a second half circuit. Each half circuit includes a first MOS transistor (M, M) as the input device and a source follower, a second MOS transistor (M, M) as a transconductance amplifier device, and a third MOS transistor (M, M) as a folded cascode device. The first half circuit receives a buffer input voltage as the input voltage and the second half circuit receives a reference voltage as the input voltage. The first and second half circuits providing a pair of differential output signals indicative of the buffer input voltage. The buffer circuit has a very low input capacitance where the input capacitance does not vary with the buffer input voltage and other operating conditions, such as fabrication process, temperature and power supply voltage variations.