The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2008

Filed:

Mar. 20, 2003
Applicants:

Philip M. Sailer, Needham, MA (US);

Nicholas Paluzzi, Hopkinton, MA (US);

Avinash Kallat, Marlborough, MA (US);

Stephen L. Scaringella, Holliston, MA (US);

Krzysztof Dobecki, Framingham, MA (US);

Inventors:

Philip M. Sailer, Needham, MA (US);

Nicholas Paluzzi, Hopkinton, MA (US);

Avinash Kallat, Marlborough, MA (US);

Stephen L. Scaringella, Holliston, MA (US);

Krzysztof Dobecki, Framingham, MA (US);

Assignee:

EMC Corporation, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); H03M 13/00 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method for determining data integrity as such data passes through a FIFO. A generator is provided for appending a bit in a predetermined bit location in each packet pushed into the FIFO in response clock signals. The appended bit is a function of the information pushed into the FIFO. A checker is provided for providing an indication of the information integrity in response to bits produced at an output of the FIFO in the predetermined bit location. In one embodiment, the generator is a parity generator and the checker is a parity checker. In one embodiment, during an initial test mode, one parity type is introduced into the FIFO by the parity generator and the opposite parity type is checked at the output of the FIFO by the parity checker to determine whether the parity checker is able to produce parity error signals. In another embodiment, the generator is a packet delimiter generator and the checker is a packet delimiter checker. In another embodiment, the generator is a frame delimiter generator and the checker is a frame delimiter checker.


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