The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 03, 2008
Filed:
Dec. 27, 2005
Ki-won Park, Gyeonggi-do, KR;
Hong-sun Hwang, Gyeonggi-do, KR;
Sung-ryul Kim, Gyeonggi-do, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A full-stress testable memory device having an open bit line architecture and a method of testing the memory device. The memory device of the invention includes dummy bit lines, and a voltage controller connected to the dummy bit lines. The voltage controller alternately provides a first variable control voltage and a second variable control voltage to the dummy bit lines during a test mode. In accordance with a method of testing the memory device, a fixed voltage is provided to the dummy bit lines of the edge sub-arrays during a normal operation mode. However, during a test mode, the fixed voltage being applied to the dummy bit line is replaced with a supply voltage and/or a ground voltage, so that all of the sub-arrays can be equally tested.