The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2008

Filed:

Jul. 14, 2005
Applicants:

Meng-hsueh Chiang, Yilan, TW;

Ching-te Kent Chuang, South Salem, NY (US);

Keunwoo Kim, Somers, NY (US);

Inventors:

Meng-Hsueh Chiang, Yilan, TW;

Ching-Te Kent Chuang, South Salem, NY (US);

Keunwoo Kim, Somers, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/20 (2006.01); H03K 19/094 (2006.01);
U.S. Cl.
CPC ...
Abstract

Techniques for employing multi-gate field effect transistors (FETS) in logic circuits formed from logic gates are provided. Double-gate transistors that conduct only when both transistor gates are active can be used to reduce the number of devices hitherto required in series or 'stacked' portions of logic gates. Circuit area can be reduced and performance can be enhanced.


Find Patent Forward Citations

Chiang, Meng-Hsueh. (2008). High-density logic techniques with reduced-stack multi-gate field effect transistors (U.S. Patent No. 7382162). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7382162

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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