The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2008

Filed:

Jun. 05, 2007
Applicants:

Byung-chul Ahn, Kumi-shi, KR;

Byoung-ho Lim, Kumi-shi, KR;

Soon-sung Yoo, Kumi-shi, KR;

Yong-wan Kim, Kumi-shi, KR;

Inventors:

Byung-chul Ahn, Kumi-shi, KR;

Byoung-ho Lim, Kumi-shi, KR;

Soon-Sung Yoo, Kumi-shi, KR;

Yong-wan Kim, Kumi-shi, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/04 (2006.01); H01L 29/10 (2006.01); H01L 31/20 (2006.01); H01L 31/036 (2006.01); H01L 31/0376 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention discloses a four-mask method of manufacturing an array substrate of a liquid crystal display device and the liquid crystal display device having the same array substrate. The method includes forming a plurality of gate lines, gate electrodes and gate extension lines by depositing a first metallic material on a substrate and patterning the first metallic material with a first mask, the gate extension lines extending toward the opposite direction of the gate electrodes; forming a first insulating layer on the whole surface having gate lines, gate electrodes, and gate extension lines; forming a plurality of data lines, source electrodes, drain electrodes, and capacitor electrodes over the gate lines by depositing a semiconductor layer, an ohmic contact layer and a second metallic material sequentially on the first insulating layer, and patterning the second metallic material and the ohmic contact layer with a second mask; forming a passivation layer and a plurality of first and second contact holes by depositing a second insulating layer on the data lines, the source electrodes, the drain electrodes and the capacitor electrodes, and patterning the second insulating layer with a third mask, the first contact holes exposing a portion of the drain electrode, the second contact holes exposing a portion of the capacitor electrodes; and forming a plurality of pixel electrodes by depositing a transparent conductive layer on the passivation layer, and patterning the transparent conductive layer by a fourth mask, the pixel electrodes contacting the drain electrodes through the first contact holes and contacting the capacitor electrodes through the second contact holes.


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