The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 03, 2008

Filed:

Mar. 11, 2005
Applicants:

Wibo Daniel Van Noort, Leuven, BE;

Eyup Aksen, Leuven, BE;

Inventors:

Wibo Daniel Van Noort, Leuven, BE;

Eyup Aksen, Leuven, BE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/31 (2006.01); H01L 21/469 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to a method of manufacturing a semiconductor device comprising a substrate () and a semiconductor body () in which at least one semiconductor element is formed, wherein, in the semiconductor body (), a semiconductor island () is formed by forming a first cavity () in the surface of the semiconductor body (), the walls of said first cavity being covered with a first dielectric layer (), after which, by means of underetching through the bottom of the cavity (), a lateral part of the semiconductor body () is removed, thereby forming a cavity () in the semiconductor body () above which the semiconductor island () is formed, and wherein a second cavity () is formed in the surface of the semiconductor body (), the walls of said second cavity being covered with a second dielectric layer, and one of the walls covered with said second dielectric layer forming a side wall of the semiconductor island (). According to the invention, the same dielectric layer () is chosen for the first and the second dielectric layer, a lateral size of the second cavity () and the thickness of the dielectric layer () are chosen such that the second cavity () becomes nearly completely filled by the dielectric layer (), and the lateral sizes of the first cavity () are chosen such that the walls and the bottom of the first cavity () are provided with a uniform coating by the dielectric layer (). In this way, a semiconductor island () which is isolated from its environment can be made using a minimum number of (masking) steps.


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