The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2008
Filed:
Dec. 19, 2005
Jerry L. Doorenbos, Tucson, AZ (US);
Dimitar Trifonov, Tucson, AZ (US);
Marco A. Gardner, Tuscon, AZ (US);
Jerry L. Doorenbos, Tucson, AZ (US);
Dimitar Trifonov, Tucson, AZ (US);
Marco A. Gardner, Tuscon, AZ (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The synchronous logic device with reduced pin count scan chain includes: more than two flip/flops coupled to form a shift register for receiving a scan data input signal; a combinational logic circuit for receiving device inputs, generating flip/flop inputs for the more than two flip/flops, and generating an output signal; a first multiplexer for providing a clock signal to the more than two flip/flops during a test mode; a second multiplexer for selecting between a test mode output from the shift register and the output signal from the combinational logic circuit, and for providing a scan data output signal; and wherein the scan data input signal and the scan data output signal share an input/output pin.