The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7380183 B1

PDF
Full Text
Expired
Date of Patent:
May. 27, 2008

Filed:

Mar. 08, 2005
Applicant:

Hiroki Machimura, Kawasaki, JP;

Inventor:

Hiroki Machimura, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor circuit apparatus, on which a scan test can be conducted, has a plurality of circuit sections. The semiconductor circuit apparatus includes a scan chain having a plurality of flip-flops for transmitting test data. The semiconductor circuit apparatus also has a first macro cell placed in a path between flip-flops included in the scan chain, a first bypass path bypassing the first macro cell, a first selection circuit selecting the first macro cell or the first bypass path, a second macro cell placed in a path between flip-flops included in the scan chain, a second bypass path bypassing the second macro cell, and a second selection circuit selecting the second macro cell or the second bypass path. The first selection circuit and the second selection circuit operate individually.


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Machimura, Hiroki. (2008). Semiconductor circuit apparatus and scan test method for semiconductor circuit (U.S. Patent No. 7380183). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7380183

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