The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2008
Filed:
Feb. 10, 2005
John Barry Griswell, Jr., Austin, TX (US);
Hung Qui Le, Austin, TX (US);
Francis Patrick O'connell, Austin, TX (US);
William J. Starke, Round Rock, TX (US);
Jeffrey Adam Stuecheli, Austin, TX (US);
Albert Thomas Williams, Austin, TX (US);
John Barry Griswell, Jr., Austin, TX (US);
Hung Qui Le, Austin, TX (US);
Francis Patrick O'Connell, Austin, TX (US);
William J. Starke, Round Rock, TX (US);
Jeffrey Adam Stuecheli, Austin, TX (US);
Albert Thomas Williams, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
In a microprocessor having a load/store unit and prefetch hardware, the prefetch hardware includes a prefetch queue containing entries indicative of allocated data streams. A prefetch engine receives an address associated with a store instruction executed by the load/store unit. The prefetch engine determines whether to allocate an entry in the prefetch queue corresponding to the store instruction by comparing entries in the queue to a window of addresses encompassing multiple cache blocks, where the window of addresses is derived from the received address. The prefetch engine compares entries in the prefetch queue to a window of 2contiguous cache blocks. The prefetch engine suppresses allocation of a new entry when any entry in the prefetch queue is within the address window. The prefetch engine further suppresses allocation of a new entry when the data address of the store instruction is equal to an address in a border area of the address window.