The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2008

Filed:

Oct. 28, 2005
Applicants:

Sheng Teng Hsu, Camas, WA (US);

Fengyan Zhang, Vancouver, WA (US);

Tingkai LI, Vancouver, WA (US);

Inventors:

Sheng Teng Hsu, Camas, WA (US);

Fengyan Zhang, Vancouver, WA (US);

Tingkai Li, Vancouver, WA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); H01L 21/8246 (2006.01); H01L 21/8247 (2006.01);
U.S. Cl.
CPC ...
Abstract

An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.


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