The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2008

Filed:

Aug. 24, 2006
Applicants:

Hiroyuki Imamura, Osaka, JP;

Nozomi Shimoishizaka, Kyoto, JP;

Inventors:

Hiroyuki Imamura, Osaka, JP;

Nozomi Shimoishizaka, Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H05K 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A wiring board includes: an insulating base; a plurality of conductive wirings; and bumps formed on the conductive wirings, respectively. The conductive wirings can be connected with electrode pads of a semiconductor element via the bumps. The conductive wirings include a connection terminal portion at an end portion opposite to the other end portion where the bumps are formed, and at the connection terminal portion, the conductive wirings can be connected with an external component. The conductive wirings include first conductive wirings and second conductive wirings, on which the bumps are formed respectively at a semiconductor element mounting region. The first conductive wirings extend from the bumps to the connection terminal portion. The second conductive wirings extend beyond the semiconductor element mounting region from the bumps but do not reach the connection terminal portion. End portions of the second conductive wirings extending beyond the semiconductor element mounting region are separated electrically from the first conductive wirings by a cutting portion formed at a boundary region with the first conductive wirings. Irrespective of the state of operating electrode pads of a semiconductor element to be mounted, the bumps can be arranged at constant intervals.


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