The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2008
Filed:
Nov. 09, 2006
Jeffrey Tyhach, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Khai Nguyen, San Jose, CA (US);
Sanjay K. Charagulla, San Jose, CA (US);
Ali Burney, Fremont, CA (US);
Jeffrey Tyhach, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Khai Nguyen, San Jose, CA (US);
Sanjay K. Charagulla, San Jose, CA (US);
Ali Burney, Fremont, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A programmable device I/O architecture allows for a variable number of I/O banks. Each I/O bank is of an I/O bank type. Each I/O bank type has a fixed number of I/O pins. I/O banks of the same I/O bank type are compatible within the same programmable device and between different types of programmable devices. The largest size I/O bank type and intermediate size I/O bank types are adapted to be a compatible supersets of every smaller I/O bank type. Support pins are regularly distributed between data pins in each I/O bank type. Multiple instances of the same or compatible I/O banks are arranged to be accessible from different sides of the programmable device. To facilitate circuit board layout, each I/O bank is arranged as a mirror and/or rotation of other I/O banks on the device.