The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2008
Filed:
Aug. 30, 2005
Akimori Hayashi, Kanagawa, JP;
Katsunobu Suzuki, Kanagawa, JP;
Ryuichi Oikawa, Kanagawa, JP;
Makoto Nakagoshi, Kanagawa, JP;
Naoko Sera, Kanagawa, JP;
Tadashi Murai, Kanagawa, JP;
Chiho Ogihara, Kanagawa, JP;
Ryohei Kataoka, Kariya, JP;
Koji Kondo, Kariya, JP;
Tomohiro Yokochi, Kariya, JP;
Akimori Hayashi, Kanagawa, JP;
Katsunobu Suzuki, Kanagawa, JP;
Ryuichi Oikawa, Kanagawa, JP;
Makoto Nakagoshi, Kanagawa, JP;
Naoko Sera, Kanagawa, JP;
Tadashi Murai, Kanagawa, JP;
Chiho Ogihara, Kanagawa, JP;
Ryohei Kataoka, Kariya, JP;
Koji Kondo, Kariya, JP;
Tomohiro Yokochi, Kariya, JP;
NEC Electronics Corporation, Kanagawa, JP;
Denso Corporation, Aichi, JP;
Abstract
A plurality of film insulators having conductive patterns that are formed on surfaces and conductive vias that pass through the film insulators in the direction of thickness are stacked together and collectively subjected to pressure and heat to be formed as a single unit. On one outermost layer of the multilayer board that has been thus formed, a plurality of connection terminals are exposed to the outside, connection bumps of an LSI chip being secured to these connection terminals. On the outermost layer of the opposite side, a multiplicity of metal pads are provided, and a solder ball is secured on each metal pad to form a ball grid array (BGA) structure for connecting to a motherboard.